Welcome to IHP-Open-DesignLib documentation!

IHP-Open-DesignLib is repository, which contains open source IC designs using IHP SG13G2 BiCMOS processs. It is also a central point for design fabrication under the concept of IHP Free MPW runs funded by a public German project FMD-QNC (16ME083). Project funds can be used exclusively to produce chip designs for non-commercial activities, such as university education, research projects, and others. In the project, a continuation for the provision of free area for the open source community is to be worked out.

Tape In date

10 May 2024

11 Nov 2024

22 Nov 2024

01 Mar 2025

09 May 2025

18 Jul 2025

15 Sep 2025

Technology

Area available [mm2]
SG13G2

10
SG13CMOS

220
SG13G2

20
SG13G2

140
SG13G2

30
SG13G2

30
SG13CMOS

220

The SG13G2 refers to the full access to the devices available in the IHP-Open-PDK. The SG13CMOS is an limited version of the SG13G2, which does not provide access to the HBT devices (High Performance Heterojunction Bipolar Transistors)

The overview of the submission process is shown on the following figure.

_images/submission_process_open_source.png

The submission process contains a few steps, where some of them are mandatory and crucial:

  1. Project development phase. At the beginning specifications an criteria will be defined by PDK status, later specifications from sponsors might be possible

  2. The community can provide designs intended for prototyping submitting a design via a pull request on an IHP-Open-DesignLib GitHub repository

  3. Once submitted a series of rejection test will be triggered checking for the completeness and correctness of the design. Usually this process takes a few hours. If the tests report errors the user will get notification in order to fix and resubmit the design.

  4. All designs, which have passed tests will be submitted for a selection process according to criteria presented below.

  5. The time window for evaluation & selection will be around 10 days (it may differ between different shuttles).

  6. Selected designs will be processed at IHP pilot line facility (clean room). This process takes around 4 to 6 months depending on the technology.

  7. IHP, as the owner of the samples, will store it in IHP Open Chip Depot. In order to promote sustainability and transparency of the results the designer or literally anyone can rent the sample for joint evaluation for a limited amount of time. The terms and conditions of this procedure are described in this document

  8. The period of joint evaluation by one person/group is limited to 2 years. The results obtained during this period should be uploaded to the respective repository under IHP-Open-DesignLib GitHub repository.

  9. Depending on the requirements, characterization can be done in scientific collaborations by the open community which may wish to use the designs for development and research projects.

Criteria for selection of designs submitted by open source community:

Mandatory criteria for IP selection

  1. Completeness of IP data. The mandatory criteria is to provide design data together with open source license.

  2. The submitted design should fulfill the DRC (Design Rule Check) criteria.

  3. The maximum area below 2 mm2 preferred (larger designs only if area is available)

  4. Potential export restrictions

Additional criteria for IP selection

  1. First time submission (preferred)

  2. Design should use tools supported by IHP open PDK

  3. For SG13G2 Runs designs using SiGe (preferred)

  4. Documentation quality

  5. Uniqueness, not yet seen designs (i.e. if there were no ADCs before, an ADC design would get a higher point)

  6. Area Utilization (designs that make more use of the padframe are preferred)

Check out the Submission process using github pull requests section for the information on how to submit a new design to the repsitory.

Note

This project is under active development.

Contents